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74LVT16373ADGG PDF预览

74LVT16373ADGG

更新时间: 2024-10-27 11:11:31
品牌 Logo 应用领域
安世 - NEXPERIA 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
13页 223K
描述
3.3 V 16-bit transparent D-type latch; 3-stateProduction

74LVT16373ADGG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.09
系列:LVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
最大电源电流(ICC):6 mA传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
Base Number Matches:1

74LVT16373ADGG 数据手册

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74LVT16373A  
3.3 V 16-bit transparent D-type latch; 3-state  
Rev. 4 — 3 August 2021  
Product data sheet  
1. General description  
The 74LVT16373A is a 16-bit D-type transparent latch with 3-state outputs. The device can be  
used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features  
two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling  
8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are  
transparent, a latch output will change each time its corresponding D-input changes. When nLE is  
LOW the latches store the information that was present at the inputs a set-up time preceding the  
HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance  
OFF-state. Operation of the nOE input does not affect the state of the latches. Bus hold data inputs  
eliminate the need for external pull-up resistors to define unused inputs  
2. Features and benefits  
16-bit transparent latch  
3-state buffers  
Wide supply voltage range from 2.7 to 3.6 V  
BiCMOS high speed and output drive  
Output capability: +64 mA/–32 mA  
Direct interface with TTL levels  
Overvoltage tolerant inputs to 5.5 V  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs  
Live insertion/extraction permitted  
Power-up reset  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B  
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)  
ESD protection:  
HBM: JESD22-A114F exceeds 2000 V  
MM: JESD22-A115-A exceeds 200 V  
Specified from -40 °C to 85 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVT16373ADGG -40 °C to +85 °C  
TSSOP48  
plastic thin shrink small outline package; 48 leads; SOT362-1  
body width 6.1 mm  
 
 
 

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