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74LVCH16244AEV-T PDF预览

74LVCH16244AEV-T

更新时间: 2024-11-02 20:07:23
品牌 Logo 应用领域
恩智浦 - NXP 电池驱动逻辑集成电路
页数 文件大小 规格书
18页 106K
描述
16-bit buffer/line driver; 5 V input/output tolerant; 3-state - Description: 3.3V 16-Bit Buffer/Line Driver; Non-Inverting with Bus Hold (3-State) ; Logic switching levels: TTL ; Number of pins: 56 BGA ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.0@3.3V ns; Voltage: 1.2-3.6

74LVCH16244AEV-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Obsolete
包装说明:FBGA, BGA56,6X10,25Reach Compliance Code:unknown
风险等级:5.75控制类型:ENABLE LOW
JESD-30 代码:R-PBGA-B56负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:4功能数量:4
端子数量:56最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA56,6X10,25
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
包装方法:TAPE AND REEL电源:3.3 V
Prop。Delay @ Nom-Sup:5.5 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BALL
端子节距:0.635 mm端子位置:BOTTOM
Base Number Matches:1

74LVCH16244AEV-T 数据手册

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74LVC16244A; 74LVCH16244A  
16-bit buffer/line driver; 5 V input/output tolerant; 3-state  
Rev. 08 — 17 November 2008  
Product data sheet  
1. General description  
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with  
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit  
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each  
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features  
I 5 V tolerant inputs/outputs for interfacing with 5 V logic  
I Wide supply voltage range from 1.2 V to 3.6 V  
I CMOS low power consumption  
I MULTIBYTE flow-through standard pin-out architecture  
I Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
I Direct interface with TTL levels  
I High-impedance when VCC = 0 V  
I All data inputs have bus hold. (74LVCH16244A only)  
I Complies with JEDEC standard JESD8-B / JESD36  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C  
 
 

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