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74LVCH16245ADGG-Q100 PDF预览

74LVCH16245ADGG-Q100

更新时间: 2024-11-25 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 140K
描述
LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48

74LVCH16245ADGG-Q100 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.57
其他特性:ALSO OPERATES AT 1.65 TO 3.6V SUPPLY系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm逻辑集成电路类型:BUS TRANSCEIVER
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):13.8 ns筛选级别:AEC-Q100
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmBase Number Matches:1

74LVCH16245ADGG-Q100 数据手册

 浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第2页浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第3页浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第4页浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第5页浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第6页浏览型号74LVCH16245ADGG-Q100的Datasheet PDF文件第7页 
74LVC16245A-Q100;  
74LVCH16245A-Q100  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Rev. 1 — 20 November 2012  
Product data sheet  
1. General description  
The 74LVC16245A-Q100; 74LVCH16245A-Q100 are 16-bit transceivers featuring  
non-inverting 3-state bus compatible outputs in both send and receive directions. The  
device features two output-enable (nOE) inputs for easy cascading and two send/receive  
(nDIR) inputs for direction control. nOE controls the outputs so that the buses are  
effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit  
transceiver. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to  
5.5 V can be applied to the outputs. These features allow the use of these devices in  
mixed 3.3 V and 5 V applications.  
The 74LVCH16245A-Q100 bus hold on data inputs eliminates the need for external  
pull-up resistors to hold unused inputs.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
MULTIBYTE flow-through standard pinout architecture  
Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
High-impedance when VCC = 0 V  
All data inputs have bus hold (74LVCH16245A-Q100 only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
 
 

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