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74LVC8T245PW PDF预览

74LVC8T245PW

更新时间: 2024-11-10 02:57:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
28页 831K
描述
8-bit dual supply translating transceiver; 3-state

74LVC8T245PW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:7.8 mm逻辑集成电路类型:BUS TRANSCEIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):32 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

74LVC8T245PW 数据手册

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74LVC8T245; 74LVCH8T245  
8-bit dual supply translating transceiver; 3-state  
Rev. 3 — 12 December 2011  
Product data sheet  
1. General description  
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with  
3-state outputs that enable bidirectional level translation. They feature two data  
input-output ports (pins An and Bn), a direction control input (DIR), an output enable input  
(OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at  
any voltage between 1.2 V and 5.5 V making the device suitable for translating between  
any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and  
DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows  
transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The  
output enable input (OE) can be used to disable the outputs so the buses are effectively  
isolated.  
The devices are fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both A port and B port are in the high-impedance OFF-state.  
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a  
valid logic level.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 1.2 V to 5.5 V  
VCC(B): 1.2 V to 5.5 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 4000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Maximum data rates:  
420 Mbps (3.3 V to 5.0 V translation)  
210 Mbps (translate to 3.3 V))  
140 Mbps (translate to 2.5 V)  
75 Mbps (translate to 1.8 V)  

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