Datasheet > 74LVC373ABQ

74LVC373ABQ

更新时间： 2024-09-29 11:14:03

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	269K
描述
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction

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74LVC373ABQ 数据手册

74LVC373A

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 5 — 27 August 2021

Product data sheet

1. General description

The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch

enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches.

In this condition the latches are transparent, a latch output will change each time its corresponding

D-input changes. When LE is LOW the latches store the information that was present at the inputs

a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to

assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the

latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Overvoltage tolerant inputs to 5.5 V

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

High-impedance outputs when V_CC= 0 V

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC373AD

-40 °C to +125 °C

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74LVC373APW -40 °C to +125 °C

74LVC373ABQ -40 °C to +125 °C

TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

SOT764-1

DHVQFN20 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 20 terminals;

body 2.5 × 4.5 × 0.85 mm

12 3 4 5 6 7...15

中文翻译

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74LVC373ABQ 替代型号

型号	品牌	替代类型	描述	数据表
SN74LVC373ARGYRG4	TI	功能相似	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVC373ARGYR	TI	功能相似	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与74LVC373ABQ相关器件

型号	品牌	获取价格	描述	数据表
74LVC373ABQ,115	NXP	获取价格	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State QFN 2
74LVC373ABQ-Q100	NEXPERIA	获取价格	Octal D-type transparent latch with 5 V tolerant
74LVC373AD	NXP	获取价格	Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State
74LVC373AD	NEXPERIA	获取价格	Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction
74LVC373AD,112	NXP	获取价格	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State SOP 2
74LVC373AD,118	NXP	获取价格	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State SOP 2
74LVC373ADB	NXP	获取价格	Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State
74LVC373ADB,112	NXP	获取价格	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State SSOP2
74LVC373ADB,118	NXP	获取价格	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State SSOP2
74LVC373ADB-Q100	NEXPERIA	获取价格	Octal D-type transparent latch with 5 V tolerant

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