Datasheet > 74LVC373A-Q100

74LVC373A-Q100

更新时间： 2024-01-17 15:44:49

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	741K
描述
Octal D-type transparent latch with 5 V tolerant

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74LVC373A-Q100 数据手册

74LVC373A-Q100

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 1 — 17 April 2013

Product data sheet

1. General description

The 74LVC373A-Q100 consists of eight D-type transparent latches, featuring separate

D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch

enable input (pin LE) and an output enable input (pin OE) are common to all internal

latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this

condition, the latches are transparent, that is, a latch output changes each time its

corresponding D-input changes. When pin LE is LOW, the latches store the information

that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of

pin LE. When pin OE is LOW, the contents of the eight latches are available at the

Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can

be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to

the outputs. These features allow the use of these devices as translators in mixed 3.3 V

and 5 V applications. The 74LVC373A-Q100 is functionally identical to the

74LVC573A-Q100, but has a different pin arrangement.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 High-impedance outputs when V_CC= 0 V

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

12 3 4 5 6 7...19

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与74LVC373A-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC373AQ20-13	DIODES	获取价格	Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, 2.50 X 4.50 MM, 0.95 MM HE
74LVC373ATTR	STMICROELECTRONICS	获取价格	OCTAL D-TYPE LATCH HIGH PERFORMANCE
74LVC373DB-T	NXP	获取价格	IC LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver
74LVC374A	STMICROELECTRONICS	获取价格	OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE
74LVC374A	NXP	获取价格	Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
74LVC374A	ONSEMI	获取价格	Low-Voltage CMOS Octal D-Type Flip-Flop
74LVC374A	DIODES	获取价格	Octal D-Type Flip-Flop with 3 State Outputs
74LVC374A_16	ONSEMI	获取价格	Low-Voltage CMOS Octal D-Type Flip-Flop
74LVC374ABQ	NEXPERIA	获取价格	Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-stateProduct
74LVC374ABQ-Q100	NEXPERIA	获取价格	Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

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