Datasheet > 74LVC2G126GT/S500

74LVC2G126GT/S500

更新时间： 2023-01-02 23:07:00

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
22页	274K
描述
Bus Driver, LVC/LCX/Z Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8

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74LVC2G126GT/S500 数据手册

74LVC2G126

Dual bus buffer/line driver; 3-state

Rev. 12 — 8 April 2013

Product data sheet

1. General description

The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each

3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE

causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all

inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G126 as a translator in a mixed 3.3 V and 5 V environment.

It is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing a damaging backflow current through the device when it is

powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...22

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型号	品牌	获取价格	描述	数据表
74LVC2G126GT-G	NXP	获取价格	LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLAS
74LVC2G126HD4-7	DIODES	获取价格	Bus Driver, LVC/LCX/Z Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8, X2-DFN2010-8
74LVC2G126-Q100	NEXPERIA	获取价格	Bus buffer/line driver; 3-state
74LVC2G132DCTRG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCT \|
74LVC2G132DCURE4	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC2G132DCURG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCU \|
74LVC2G132DCUTE4	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC2G132DCUTG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCU \|
74LVC2G14	NXP	获取价格	Dual inverting Schmitt-trigger with 5 V tolerant input
74LVC2G14	DIODES	获取价格	DUAL SCHMITT TRIGGER INVERTER