Datasheet > 74LVC2G126-Q100

74LVC2G126-Q100

更新时间： 2024-01-10 01:14:53

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
12页	212K
描述
Bus buffer/line driver; 3-state

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数据手册

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74LVC2G126-Q100 数据手册

74LVC2G126-Q100

Bus buffer/line driver; 3-state

Rev. 3 — 10 January 2019

Product data sheet

1. General description

The 74LVC2G126-Q100 is a dual non-inverting buffer/line driver with 3-state outputs. An output

enable input (pin nOE) controls each 3-state output. A LOW-level at pin nOE causes the output to

assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly

tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G126-Q100 as a translator in a mixed 3.3 V and 5 V environment.

It is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry disables the

output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant input/output for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

±24 mA output drive (V_CC= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC2G126DP-Q100 -40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads; SOT505-2

body width 3 mm; lead length 0.5 mm

74LVC2G126DC-Q100 -40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

12 3 4 5 6 7...12

中文翻译

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与74LVC2G126-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC2G132DCTRG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCT \|
74LVC2G132DCURE4	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC2G132DCURG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCU \|
74LVC2G132DCUTE4	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC2G132DCUTG4	TI	获取价格	具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门 \| DCU \|
74LVC2G14	NXP	获取价格	Dual inverting Schmitt-trigger with 5 V tolerant input
74LVC2G14	DIODES	获取价格	DUAL SCHMITT TRIGGER INVERTER
74LVC2G14	SGMICRO	获取价格	Dual Inverter with 5V Tolerant Schmitt Trigger Inputs
74LVC2G14DW	DIODES	获取价格	DUAL SCHMITT TRIGGER INVERTER
74LVC2G14DW-7	DIODES	获取价格	DUAL SCHMITT TRIGGER INVERTER

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