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74LVC245A_04 PDF预览

74LVC245A_04

更新时间: 2024-11-11 04:47:51
品牌 Logo 应用领域
恩智浦 - NXP 总线收发器
页数 文件大小 规格书
12页 307K
描述
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (NOT INVERTED) HIGH PERFORMANCE

74LVC245A_04 数据手册

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74LVC245A  
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER  
(NOT INVERTED) HIGH PERFORMANCE  
5V TOLERANT INPUTS  
HIGH SPEED: t = 6.3ns (MAX.) at V = 3V  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
PD  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN) at V = 3V  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
OH  
OL  
CC  
SOP  
TSSOP  
t
t
PLH  
PHL  
Table 1: Order Codes  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 1.65V to 3.6V (1.2V Data  
V
T & R  
CC  
Retention)  
SOP  
74LVC245AMTR  
74LVC245ATTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 245  
TSSOP  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
It has more speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
All inputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD  
immunity and transient excess voltage.  
All floating bus terminals during High Z State must  
be held HIGH or LOW.  
DESCRIPTION  
The 74LVC245A is a low voltage CMOS OCTAL  
BUS TRANSCEIVER (3-STATE) fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology. It is ideal for 1.65 to 3.6  
V
operations and low power and low noise  
CC  
applications.  
This IC is intended for two-way asynchronous  
communication between data buses and the  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/12  
July 2004  
.

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