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74LVC245ABX,115 PDF预览

74LVC245ABX,115

更新时间: 2024-11-11 15:29:43
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路
页数 文件大小 规格书
18页 137K
描述
74LVC(H)245A - Octal bus transceiver; 3-state QFN 20-Pin

74LVC245ABX,115 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFN
包装说明:HVQCCN, LCC20,.1X.18,20针数:20
Reach Compliance Code:compliant风险等级:8
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PQCC-N20JESD-609代码:e4
长度:4.5 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC20,.1X.18,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:0.5 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:2.5 mmBase Number Matches:1

74LVC245ABX,115 数据手册

 浏览型号74LVC245ABX,115的Datasheet PDF文件第2页浏览型号74LVC245ABX,115的Datasheet PDF文件第3页浏览型号74LVC245ABX,115的Datasheet PDF文件第4页浏览型号74LVC245ABX,115的Datasheet PDF文件第5页浏览型号74LVC245ABX,115的Datasheet PDF文件第6页浏览型号74LVC245ABX,115的Datasheet PDF文件第7页 
74LVC245A; 74LVCH245A  
Octal bus transceiver; 3-state  
Rev. 8 — 28 June 2013  
Product data sheet  
1. General description  
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus  
compatible outputs in both send and receive directions. The device features an output  
enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.  
OE controls the outputs so that the buses are effectively isolated.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Inputs accept voltages up to 5.5 V  
High-impedance when VCC = 0 V  
Bus hold on all data inputs (74LVCH245A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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