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74LVC245APW-Q100 PDF预览

74LVC245APW-Q100

更新时间: 2023-09-03 20:28:18
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
15页 258K
描述
Octal bus transceiver; 3-stateProduction

74LVC245APW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP2包装说明:TSSOP,
针数:20Reach Compliance Code:compliant
风险等级:5.61其他特性:ALSO OPERATES AT 1.65 TO 3.6V SUPPLY
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):16.9 ns筛选级别:AEC-Q100
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LVC245APW-Q100 数据手册

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74LVC245A-Q100;  
74LVCH245A-Q100  
Octal bus transceiver; 3-state  
Rev. 4 — 5 August 2020  
Product data sheet  
1. General description  
The 74LVC245A-Q100; 74LVCH245A-Q100 is an 8-bit transceiver with 3-state outputs. The device  
features an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes  
the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or  
5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V  
environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Overvoltage tolerant inputs to 5.5 V  
Bus hold on all data inputs (74LVCH245A-Q100 only)  
IOFF circuitry provides partial Power-down mode operation  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of  
solder joints  
 
 

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