Datasheet > 74LVC161BQ

74LVC161BQ

更新时间： 2024-11-19 11:15:31

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	293K
描述
Presettable synchronous 4-bit binary counter; asynchronous resetProduction

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74LVC161BQ 数据手册

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous

reset

Rev. 7 — 22 September 2021

Product data sheet

1. General description

The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the

positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH

or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the

data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the

clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW

at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE,

CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies

serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed

forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH

output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to

enable the next cascaded stage.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

2. Features and benefits

•

Overvoltage tolerant inputs to 5.5 V

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power dissipation

Direct interface with TTL levels

Asynchronous reset

Synchronous counting and loading

Two count enable inputs for n-bit cascading

Positive edge-triggered clock

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...19

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与74LVC161BQ相关器件

型号	品牌	获取价格	描述	数据表
74LVC161D	NXP	获取价格	Presettable synchronous 4-bit binary counter; asynchronous reset
74LVC161D	NEXPERIA	获取价格	Presettable synchronous 4-bit binary counter; asynchronous resetProduction
74LVC161D,118	NXP	获取价格	74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset SOP 16-Pin
74LVC161DB	NXP	获取价格	Presettable synchronous 4-bit binary counter; asynchronous reset
74LVC161DB,112	NXP	获取价格	74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset SSOP1 16-Pin
74LVC161DB,118	NXP	获取价格	74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset SSOP1 16-Pin
74LVC161DB-T	NXP	获取价格	IC LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, 5.30 MM,
74LVC161D-T	NXP	获取价格	IC LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, 3.90 MM,
74LVC161PW	NXP	获取价格	Presettable synchronous 4-bit binary counter; asynchronous reset
74LVC161PW	NEXPERIA	获取价格	Presettable synchronous 4-bit binary counter; asynchronous resetProduction

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