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74LVC162244ADGG.518 PDF预览

74LVC162244ADGG.518

更新时间： 2024-11-18 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件
页数 文件大小 规格书
15页 166K
描述
LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48

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74LVC162244ADGG.518 技术参数

生命周期：Transferred包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.6系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G48长度：12.5 mm
逻辑集成电路类型：BUS DRIVER位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：8.5 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.2 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

74LVC162244ADGG.518 数据手册

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74LVC162244A; 74LVCH162244A  
16-bit buffer/line driver; 30 series termination resistors; 5 V  
tolerant input/output; 3-state  
Rev. 6 — 16 December 2011  
Product data sheet  
1. General description  
The 74LVC162244A; 74LVCH162244A are 16-bit non-inverting buffer/line drivers with  
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit  
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each  
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state. The device is designed with 30 series termination resistors  
in both HIGH and LOW output stages to reduce line noise.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH162244A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
High-impedance when VCC = 0 V  
All data inputs have bus hold. (74LVCH162244A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
1234567...15

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