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74LVC161PW-T PDF预览

74LVC161PW-T

更新时间： 2024-11-18 20:31:43
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
22页 161K
描述
IC LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, Counter

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74LVC161PW-T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.09Is Samacsys：N
其他特性：TCO OUTPUT计数方向：UP
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：9.5 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：150 MHz
Base Number Matches：1

74LVC161PW-T 数据手册

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74LVC161  
Presettable synchronous 4-bit binary counter; asynchronous  
reset  
Rev. 6 — 30 September 2013  
Product data sheet  
1. General description  
The 74LVC161 is a synchronous presettable binary counter which features an internal  
look-ahead carry and can be used for high-speed counting. Synchronous operation is  
provided by having all flip-flops clocked simultaneously on the positive-going edge of the  
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level  
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting  
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter  
on the positive-going edge of the clock (provided that the set-up and hold time  
requirements for PE are met). Preset takes place regardless of the levels at count enable  
inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four  
outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins  
CP, PE, CET and CEP (thus providing an asynchronous clear function).  
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs  
(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the  
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output  
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be  
used to enable the next cascaded stage.  
The maximum clock frequency for the cascaded counters is determined by tPHL  
(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:  
1
fmax  
=
-----------------------------------  
t
PHLmax+ tsu  
It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to  
most advanced CMOS compatible TTL families.  
2. Features and benefits  
5 V tolerant inputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Asynchronous reset  
Synchronous counting and loading  
Two count enable inputs for n-bit cascading  
Positive edge-triggered clock  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
 
 
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