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74LVC162244ADGG PDF预览

74LVC162244ADGG

更新时间: 2024-11-19 11:14:27
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 244K
描述
16-bit buffer/line driver; 30 Ω series termination resistors; 5 V tolerant input/output; 3-stateProduction

74LVC162244ADGG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:12.5 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):17.2 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmBase Number Matches:1

74LVC162244ADGG 数据手册

 浏览型号74LVC162244ADGG的Datasheet PDF文件第2页浏览型号74LVC162244ADGG的Datasheet PDF文件第3页浏览型号74LVC162244ADGG的Datasheet PDF文件第4页浏览型号74LVC162244ADGG的Datasheet PDF文件第5页浏览型号74LVC162244ADGG的Datasheet PDF文件第6页浏览型号74LVC162244ADGG的Datasheet PDF文件第7页 
74LVC162244A; LVCH162244A  
16-bit buffer/line driver; 30 Ω series termination resistors;  
5 V tolerant input/output; 3-state  
Rev. 8 — 23 September 2021  
Product data sheet  
1. General description  
The 74LVC162244A; 74LVCH162244A is a 16-bit buffer/line driver with 30 Ω termination resistors  
and 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit  
buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of  
the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
The 74LVCH162244A bus hold on data inputs eliminates the need for external pull-up resistors to  
hold unused inputs.  
2. Features and benefits  
Overvoltage tolerant inputs to 5.5 V  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power dissipation  
Multibyte flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground bounce  
Direct interface with TTL levels  
IOFF circuitry provides partial Power-down mode operation  
All data inputs have bus hold. (74LVCH162244A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

74LVC162244ADGG 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC16244ADGG TI

类似代替

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74LVCH162244AGR TI

类似代替

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74LVC162244ADGGR TI

功能相似

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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