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74LV00A PDF预览

74LV00A

更新时间: 2024-11-18 04:01:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
14页 409K
描述
QUADRUPLE 2 INPUT POSITIVE NAND GATES

74LV00A 数据手册

 浏览型号74LV00A的Datasheet PDF文件第2页浏览型号74LV00A的Datasheet PDF文件第3页浏览型号74LV00A的Datasheet PDF文件第4页浏览型号74LV00A的Datasheet PDF文件第5页浏览型号74LV00A的Datasheet PDF文件第6页浏览型号74LV00A的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆ ꢇ  
SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005  
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 6.5 ns at 5 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
− 1000-V Charged-Device Model (C101)  
SN54LV00A . . . J OR W PACKAGE  
SN74LV00A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
SN74LV00A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV00A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
4B  
4A  
4Y  
3B  
3A  
3Y  
1B  
1Y  
2A  
2B  
2Y  
13 4B  
12 4A  
2
3
4
5
6
17  
16  
15  
14  
11  
10  
9
4Y  
3B  
3A  
NC  
2B  
2Y  
GND  
9 10 11 12 13  
8
7
8
NC − No internal connection  
description/ordering information  
These quadruple 2-input positive-NAND gates are designed for 2-V to 5.5-V V  
operation.  
CC  
The ’LV00A devices perform the Boolean function Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Reel of 1000  
Tube of 50  
SN74LV00ARGYR  
SN74LV00AD  
LV00A  
LV00A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV00ADR  
SN74LV00ANSR  
SN74LV00ADBR  
SN74LV00APW  
SN74LV00APWR  
SN74LV00APWT  
SN74LV00ADGVR  
SNJ54LV00AJ  
SOP − NS  
74LV00A  
LV00A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV00A  
TVSOP − DGV  
CDIP − J  
LV00A  
SNJ54LV00AJ  
SNJ54LV00AW  
SNJ54LV00AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV00AW  
SNJ54LV00AFK  
LCCC - FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢋ ꢁ ꢄꢏꢀꢀ ꢔ ꢓꢖ ꢏꢍꢗ ꢒꢀ ꢏ ꢁ ꢔꢓꢏꢌ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢎꢍ ꢔ ꢌ ꢋ ꢤꢓ ꢒꢔ ꢁ  
ꢧꢣ ꢦ ꢣ ꢠ ꢡ ꢘ ꢡ ꢦ ꢛ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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