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74LV00PW,118 PDF预览

74LV00PW,118

更新时间: 2024-02-16 00:30:51
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 90K
描述
74LV00 - Quad 2-input NAND gate TSSOP 14-Pin

74LV00PW,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.39
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.006 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:18 ns
传播延迟(tpd):31 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74LV00PW,118 数据手册

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74LV00  
Quad 2-input NAND gate  
Rev. 03 — 20 December 2007  
Product data sheet  
1. General description  
The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with  
74HC00 and 74HCT00.  
The 74LV00 provides a quad 2-input NAND function.  
2. Features  
Wide operating voltage: 1.0 V to 5.5 V  
Optimized for low voltage applications: 1.0 V to 3.6 V  
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LV00N  
74LV00D  
40 °C to +125 °C  
40 °C to +125 °C  
DIP14  
SO14  
plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
SOT108-1  
plastic small outline package; 14 leads;  
body width 3.9 mm  
74LV00DB  
74LV00PW  
74LV00BQ  
40 °C to +125 °C  
40 °C to +125 °C  
40 °C to +125 °C  
SSOP14  
plastic shrink small outline package; 14 leads;  
body width 5.3 mm  
SOT337-1  
SOT402-1  
SOT762-1  
TSSOP14  
plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
DHVQFN14 plastic dual in-line compatible thermal enhanced very  
thin quad flat package; no leads; 14 terminals;  
body 2.5 × 3 × 0.85 mm  
 
 
 

74LV00PW,118 替代型号

型号 品牌 替代类型 描述 数据表
74LV00PW NXP

完全替代

Quad 2-input NAND gate

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