74LCX125M_NL

更新时间： 2024-11-04 13:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
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中文翻译

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数据手册

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74LCX125M_NL 数据手册

March 1995

Revised April 1999

74LCX125

Low Voltage Quad Buffer

with 5V Tolerant Inputs and Outputs

■ 6.0 ns t_PDmax (V_CC= 3.3V), 10 µA I_CCmax

General Description

The LCX125 contains four independent non-inverting buff-

ers with 3-STATE outputs. The inputs tolerate voltages up

to 7V allowing the interface of 5V systems to 3V systems.

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ ±24 mA output drive (V_CC= 3.0V)

The 74LCX125 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model > 2000V

Features

■ 5V tolerant inputs and outputs

Machine model > 100V

Note 1: To ensure the high-impedance state during power up or down, OE

■ 2.3V–3.6V V_CCspecifications provided

should be tied to V

through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Order Number Package Number

Package Description

74LCX125M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX125SJ

74LCX125MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Truth Table

Pin Descriptions

Inputs

Output

O_n

Pin Names

Description

Inputs

OE_n

A_n

OE_n

O_n

Output Enable Inputs

Outputs

H = HIGH Voltage Level

L = LOW Voltage Level

Z = High Impedance

X = Immaterial

DS012416.prf

www.fairchildsemi.com

12 3 4 5 6 7

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