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74HCT74BQ,115 PDF预览

74HCT74BQ,115

更新时间: 2024-02-27 17:36:28
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路触发器
页数 文件大小 规格书
21页 174K
描述
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger QFN 14-Pin

74HCT74BQ,115 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN,
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.47
系列:HCTJESD-30 代码:R-PQCC-N14
JESD-609代码:e4长度:3 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):53 ns
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:2.5 mm最小 fmax:18 MHz
Base Number Matches:1

74HCT74BQ,115 数据手册

 浏览型号74HCT74BQ,115的Datasheet PDF文件第2页浏览型号74HCT74BQ,115的Datasheet PDF文件第3页浏览型号74HCT74BQ,115的Datasheet PDF文件第4页浏览型号74HCT74BQ,115的Datasheet PDF文件第5页浏览型号74HCT74BQ,115的Datasheet PDF文件第6页浏览型号74HCT74BQ,115的Datasheet PDF文件第7页 
74HC74; 74HCT74  
Dual D-type flip-flop with set and reset; positive edge-trigger  
Rev. 4 — 27 August 2012  
Product data sheet  
1. General description  
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have  
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary  
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time  
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at  
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to  
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC74: CMOS level  
For 74HCT74: TTL level  
Symmetrical output impedance  
Low power dissipation  
High noise immunity  
Balanced propagation delays  
Specified in compliance with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
3. Ordering information  
Table 1.  
Type number Package  
Temperature range Name  
Ordering information  
Description  
Version  
74HC74N  
40 C to +125 C  
DIP14  
plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
74HCT74N  
74HC74D  
40 C to +125 C  
40 C to +125 C  
SO14  
plastic small outline package; 14 leads; body width  
3.9 mm  
SOT108-1  
74HCT74D  
74HC74DB  
74HCT74DB  
SSOP14  
plastic shrink small outline package; 14 leads; body SOT337-1  
width 5.3 mm  
 
 
 

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