5秒后页面跳转
74HCT74N,652 PDF预览

74HCT74N,652

更新时间: 2024-09-27 15:30:59
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
21页 188K
描述
74HCT74N

74HCT74N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.78
系列:HCTJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.025 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:18000000 Hz最大I(ol):0.004 A
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:4.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:18 MHz
Base Number Matches:1

74HCT74N,652 数据手册

 浏览型号74HCT74N,652的Datasheet PDF文件第2页浏览型号74HCT74N,652的Datasheet PDF文件第3页浏览型号74HCT74N,652的Datasheet PDF文件第4页浏览型号74HCT74N,652的Datasheet PDF文件第5页浏览型号74HCT74N,652的Datasheet PDF文件第6页浏览型号74HCT74N,652的Datasheet PDF文件第7页 
74HC74; 74HCT74  
Dual D-type flip-flop with set and reset; positive edge-trigger  
Rev. 4 — 27 August 2012  
Product data sheet  
1. General description  
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have  
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary  
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time  
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at  
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to  
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC74: CMOS level  
For 74HCT74: TTL level  
Symmetrical output impedance  
Low power dissipation  
High noise immunity  
Balanced propagation delays  
Specified in compliance with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
3. Ordering information  
Table 1.  
Type number Package  
Temperature range Name  
Ordering information  
Description  
Version  
74HC74N  
40 C to +125 C  
DIP14  
plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
74HCT74N  
74HC74D  
40 C to +125 C  
40 C to +125 C  
SO14  
plastic small outline package; 14 leads; body width  
3.9 mm  
SOT108-1  
74HCT74D  
74HC74DB  
74HCT74DB  
SSOP14  
plastic shrink small outline package; 14 leads; body SOT337-1  
width 5.3 mm  
 
 
 

74HCT74N,652 替代型号

型号 品牌 替代类型 描述 数据表
MC74HCT74ADR2G ONSEMI

功能相似

Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs
MC74HCT74ADG ONSEMI

功能相似

Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs

与74HCT74N,652相关器件

型号 品牌 获取价格 描述 数据表
74HCT74N-B PHILIPS

获取价格

D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDIP14
74HCT74PW NXP

获取价格

Dual D-type flip-flop with set and reset; positive-edge trigger
74HCT74PW NEXPERIA

获取价格

Dual D-type flip-flop with set and reset; positive edge-triggerProduction
74HCT74PW,112 NXP

获取价格

74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin
74HCT74PW-Q100 NEXPERIA

获取价格

Dual D-type flip-flop with set and reset; positive edge-trigger
74HCT74PW-T NXP

获取价格

暂无描述
74HCT74-Q100 NEXPERIA

获取价格

Dual D-type flip-flop with set and reset; positive edge-trigger
74HCT75 NXP

获取价格

Quad bistable transparent latch
74HCT7540 NXP

获取价格

Octal Schmitt trigger buffer/line driver; 3-state; inverting
74HCT7540D NEXPERIA

获取价格

Octal Schmitt trigger buffer/line driver; 3-state; invertingProduction