Datasheet > 74HCT74-Q100

74HCT74-Q100

更新时间： 2024-11-12 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	798K
描述
Dual D-type flip-flop with set and reset; positive edge-trigger

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74HCT74-Q100 数据手册

74HC74-Q100; 74HCT74-Q100

Dual D-type flip-flop with set and reset; positive edge-trigger

Rev. 3 — 4 December 2015

Product data sheet

1. General description

The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with

individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time

requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and

appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit

highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC74-Q100: CMOS level

 For 74HCT74-Q100: TTL level

 Symmetrical output impedance

 Low power dissipation

 High noise immunity

 Balanced propagation delays

 Specified in compliance with JEDEC standard no. 7A

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...19

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