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74HCT373D,653 PDF预览

74HCT373D,653

更新时间: 2024-11-12 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
26页 132K
描述
74HC(T)373 - Octal D-type transparent latch; 3-state SOP 20-Pin

74HCT373D,653 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.53
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):48 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

74HCT373D,653 数据手册

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74HC373; 74HCT373  
Octal D-type transparent latch; 3-state  
Rev. 03 — 20 January 2006  
Product data sheet  
1. General description  
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type  
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)  
input and an output enable (OE) input are common to all latches.  
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true  
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the  
latches are transparent, i.e. a latch output will change state each time its corresponding  
D input changes.  
When LE is LOW the latches store the information that was present at the D inputs a  
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents  
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-  
impedance OFF-state. Operation of the OE input does not affect the state of the latches.  
The 74HC373; 74HCT373 is functionally identical to:  
74HC533; 74HCT533: but inverted outputs  
74HC563; 74HCT563: but inverted outputs and different pin arrangement  
74HC573; 74HCT573: but different pin arrangement  
2. Features  
3-state non-inverting outputs for bus oriented applications  
Common 3-state output enable input  
Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and  
74HC533; 74HCT533  
ESD protection:  
HBM EIA/JESD22-A114-C exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

74HCT373D,653 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT373DWR TI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74HCT373DW TI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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