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74HCT373D-Q100 PDF预览

74HCT373D-Q100

更新时间: 2024-11-13 11:10:27
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 272K
描述
Octal D-type transparent latch; 3-stateProduction

74HCT373D-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.59
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):48 ns筛选级别:AEC-Q100
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74HCT373D-Q100 数据手册

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74HC373-Q100; 74HCT373-Q100  
Octal D-type transparent latch; 3-state  
Rev. 2 — 22 July 2020  
Product data sheet  
1. General description  
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs.  
The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at  
the inputs enter the latches. In this condition the latches are transparent, a latch output will change  
each time its corresponding D-input changes. When LE is LOW the latches store the information  
that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH  
on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does  
not affect the state of the latches. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Input levels:  
For 74HC373-Q100: CMOS level  
For 74HCT373-Q100: TTL level  
3-state non-inverting outputs for bus-oriented applications  
Common 3-state output enable input  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Multiple package options  
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of  
solder joints  
 
 

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