是否Rohs认证: | 符合 | 生命周期: | Active |
包装说明: | SOP, | Reach Compliance Code: | compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.2 |
系列: | HCT | JESD-30 代码: | R-PDSO-G14 |
JESD-609代码: | e4 | 长度: | 8.65 mm |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | J-K FLIP-FLOP |
湿度敏感等级: | 1 | 位数: | 2 |
功能数量: | 2 | 端子数量: | 14 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
输出极性: | COMPLEMENTARY | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SOP | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 峰值回流温度(摄氏度): | 260 |
传播延迟(tpd): | 54 ns | 认证状态: | Not Qualified |
座面最大高度: | 1.75 mm | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子面层: | Nickel/Palladium/Gold (Ni/Pd/Au) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 30 |
触发器类型: | NEGATIVE EDGE | 宽度: | 3.9 mm |
最小 fmax: | 60 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74HCT107D,653 | NXP |
获取价格 |
74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger SOIC 14-Pin | |
74HCT107DB | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74HCT107DB-T | NXP |
获取价格 |
暂无描述 | |
74HCT107D-Q100 | NEXPERIA |
获取价格 |
Dual JK flip-flop with reset; negative-edge triggerProduction | |
74HCT107D-T | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74HCT107N | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74HCT107N-B | PHILIPS |
获取价格 |
J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDIP14 | |
74HCT107PW | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74HCT109 | NXP |
获取价格 |
Dual JK flip-flop with set and reset; positive-edge trigger | |
74HCT109D | NXP |
获取价格 |
Dual JK flip-flop with set and reset; positive-edge trigger |