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74HCT107D PDF预览

74HCT107D

更新时间: 2024-11-25 11:12:15
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
15页 254K
描述
Dual JK flip-flop with reset; negative-edge triggerProduction

74HCT107D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.2
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
湿度敏感等级:1位数:2
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):54 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:60 MHzBase Number Matches:1

74HCT107D 数据手册

 浏览型号74HCT107D的Datasheet PDF文件第2页浏览型号74HCT107D的Datasheet PDF文件第3页浏览型号74HCT107D的Datasheet PDF文件第4页浏览型号74HCT107D的Datasheet PDF文件第5页浏览型号74HCT107D的Datasheet PDF文件第6页浏览型号74HCT107D的Datasheet PDF文件第7页 
74HC107; 74HCT107  
Dual JK flip-flop with reset; negative-edge trigger  
Rev. 6 — 7 July 2021  
Product data sheet  
1. General description  
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and  
K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an  
asynchronous active LOW input and operates independently of the clock input. The J and K inputs  
control the state changes of the flip-flops as described in the mode select function table. The J and  
K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable  
operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface  
inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Input levels:  
The 74HC107: CMOS levels  
The 74HCT107: TTL levels  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC107D  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74HCT107D  
74HC107PW  
TSSOP14  
plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
SOT402-1  
 
 
 

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