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74HC75D PDF预览

74HC75D

更新时间: 2024-11-24 11:10:31
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 253K
描述
Quad bistable transparant latchProduction

74HC75D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.16
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
逻辑集成电路类型:D LATCH湿度敏感等级:1
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):190 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:HIGH LEVEL宽度:3.9 mm
Base Number Matches:1

74HC75D 数据手册

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74HC75  
Quad bistable transparant latch  
Rev. 5 — 17 March 2021  
Product data sheet  
1. General description  
The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are  
simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn  
is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data  
inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior  
to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain  
stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Complementary Q and Q outputs  
VCC and GND on the center pins  
CMOS input levels  
ESD protection:  
HBM EIA/JESD22-A114F exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +80 °C and from -40 °C to +125 °C.  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +125 °C  
Name  
Description  
Version  
74HC75D  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74HC75PW  
-40 °C to +125 °C  
TSSOP16  
plastic thin shrink small outline package;  
16 leads; body width 4.4 mm  
SOT403-1  
 
 
 

74HC75D 替代型号

型号 品牌 替代类型 描述 数据表
74HC109D,652 NXP

类似代替

74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger SOP 16-Pin
74HCT173D,652 NXP

功能相似

74HC(T)173 - Quad D-type flip-flop; positive-edge trigger; 3-state SOP 16-Pin

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