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74HC75DB PDF预览

74HC75DB

更新时间: 2024-11-26 12:54:19
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 87K
描述
Quad bistable transparant latch

74HC75DB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SSOP
包装说明:SSOP, SSOP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.35系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:6.2 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.004 A
湿度敏感等级:1位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:36 ns传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:HIGH LEVEL宽度:5.3 mm
最小 fmax:60 MHzBase Number Matches:1

74HC75DB 数据手册

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74HC75  
Quad bistable transparant latch  
Rev. 03 — 12 November 2004  
Product data sheet  
1. General description  
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power  
Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by  
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data  
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs  
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time  
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched  
outputs remain stable as long as the LEnn is LOW.  
2. Features  
Complementary Q and Q outputs  
VCC and GND on the center pins  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  

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