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74HC373BQ-Q100,115 PDF预览

74HC373BQ-Q100,115

更新时间： 2024-11-28 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
24页 182K
描述
74HC(T)373-Q100 - Octal D-type transparent latch; 3-state QFN 20-Pin

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74HC373BQ-Q100,115 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFN包装说明：2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT764-1, DHVQFN-20
针数：20Reach Compliance Code：compliant
风险等级：5.78Base Number Matches：1

74HC373BQ-Q100,115 数据手册

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74HC373-Q100; 74HCT373-Q100  
Octal D-type transparent latch; 3-state  
Rev. 1 — 10 August 2012  
Product data sheet  
1. General description  
The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin  
compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring  
separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A  
latch enable (LE) input and an output enable (OE) input are common to all latches.  
The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with  
3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this  
condition the latches are transparent, i.e. a latch output changes state each time its  
corresponding D input changes.  
When LE is LOW, the latches store the information that was present at the D inputs a  
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents  
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-  
impedance OFF-state. Operation of the OE input does not affect the state of the latches.  
The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:  
• 74HC573-Q100; 74HCT573-Q100: but different pin arrangement  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Input levels:  
For 74HC373-Q100: CMOS level  
For 74HCT373-Q100: TTL level  
3-state non-inverting outputs for bus-oriented applications  
Common 3-state output enable input  
Functionally identical to the 74HC573-Q100; 74HCT573-Q100  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
 
 
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