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74HC374 PDF预览

74HC374

更新时间: 2024-11-29 17:01:27
品牌 Logo 应用领域
圣邦微 - SGMICRO /
页数 文件大小 规格书
12页 606K
描述
Octal D-Type Positive Edge-Triggered Flip-Flop with 3-State Outputs

74HC374 数据手册

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74HC374  
Octal D-Type Positive Edge-Triggered  
Flip-Flop with 3-State Outputs  
GENERAL DESCRIPTION  
FEATURES  
The 74HC374 is an 8-bit D-type positive edge-triggered  
flip-flop with 3-state outputs that is designed for 2.0V to  
5.5V VCC operation.  
Wide Operating Voltage Range: 2.0V to 5.5V  
+7.8mA/-7.8mA Output Current  
CMOS Low Power Consumption  
Support Octal Bus Interface  
The device is provided with a clock (CP) input and an  
3-State Non-Inverting Outputs  
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output enable (OE) input. When data at the Dn input  
8-Bit Positive Edge-Triggered Register  
3-State Buffer and Independent Register  
-40to +125Operating Temperature Range  
Available in Green SOIC-20 and TSSOP-20  
Packages  
suffices for setup and hold time purposes, data can be  
moved to the Qn output on the low-to-high clock  
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transition. When OE is high, all outputs are in  
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high-impedance state. OE has no influence on the state  
of the flip-flops.  
The clamp diodes of inputs allow the use of current  
limiting resistors to connect inputs to the voltage  
exceeding supply voltage.  
FUNCTION TABLE  
INPUT  
OUTPUT  
INTERNAL  
FLIP-FLOPS  
The 74HC374 is available in Green SOIC-20 and  
TSSOP-20 packages. It operates over an ambient  
temperature range of -40to +125.  
�����  
CP  
Dn  
I
Qn  
L
OE  
L
L
L
H
L
h
I
H
Z
H
H
h
H
Z
LOGIC DIAGRAM  
H = High voltage level.  
h = High voltage level one setup time before clock rising edge .  
L = Low voltage level.  
D2 to D6  
D0  
D1  
D7  
D
D
D
I = Low voltage level one setup time before clock rising edge .  
Z = High-impedance state.  
CP Q  
CP Q  
CP Q  
= Low-to-high clock transition.  
CP  
OE  
Q0  
Q1  
Q7  
Q2 to Q6  
SG Micro Corp  
www.sg-micro.com  
NOVEMBER 2023 – REV. A  

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