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74HC373PW/T3 PDF预览

74HC373PW/T3

更新时间: 2024-11-29 03:33:19
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件
页数 文件大小 规格书
26页 147K
描述
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20

74HC373PW/T3 数据手册

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74HC373; 74HCT373  
Octal D-type transparent latch; 3-state  
Rev. 03 — 20 January 2006  
Product data sheet  
1. General description  
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type  
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)  
input and an output enable (OE) input are common to all latches.  
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true  
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the  
latches are transparent, i.e. a latch output will change state each time its corresponding  
D input changes.  
When LE is LOW the latches store the information that was present at the D inputs a  
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents  
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-  
impedance OFF-state. Operation of the OE input does not affect the state of the latches.  
The 74HC373; 74HCT373 is functionally identical to:  
74HC533; 74HCT533: but inverted outputs  
74HC563; 74HCT563: but inverted outputs and different pin arrangement  
74HC573; 74HCT573: but different pin arrangement  
2. Features  
3-state non-inverting outputs for bus oriented applications  
Common 3-state output enable input  
Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and  
74HC533; 74HCT533  
ESD protection:  
HBM EIA/JESD22-A114-C exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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