Datasheet > 74HC373D-Q100

74HC373D-Q100

更新时间： 2024-11-28 12:50:43

品牌	Logo	应用领域
恩智浦 - NXP		锁存器逻辑集成电路光电二极管驱动
页数	文件大小	规格书
24页	179K
描述
Octal D-type transparent latch; 3-state

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74HC373D-Q100 数据手册

74HC373-Q100; 74HCT373-Q100

Octal D-type transparent latch; 3-state

Rev. 1 — 10 August 2012

Product data sheet

1. General description

The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC

standard no. 7A.

The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring

separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A

latch enable (LE) input and an output enable (OE) input are common to all latches.

The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with

3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this

condition the latches are transparent, i.e. a latch output changes state each time its

corresponding D input changes.

When LE is LOW, the latches store the information that was present at the D inputs a

set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents

of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-

impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:

• 74HC573-Q100; 74HCT573-Q100: but different pin arrangement

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC373-Q100: CMOS level

 For 74HCT373-Q100: TTL level

 3-state non-inverting outputs for bus-oriented applications

 Common 3-state output enable input

 Functionally identical to the 74HC573-Q100; 74HCT573-Q100

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...24

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与74HC373D-Q100相关器件

型号	品牌	获取价格	描述	数据表
74HC373D-T	PHILIPS	获取价格	D Latch, 1-Func, 8-Bit, CMOS, PDSO20
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74HC373DTR2G	ONSEMI	获取价格	Octal 3−State Non−Inverting Transparent Latch
74HC373N	NXP	获取价格	Octal D-type transparent latch; 3-state
74HC373PW	NXP	获取价格	Octal D-type transparent latch; 3-state
74HC373PW	NEXPERIA	获取价格	Octal D-type transparent latch; 3-stateProduction
74HC373PW/T3	NXP	获取价格	HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSO
74HC373PW-Q100	NXP	获取价格	Octal D-type transparent latch; 3-state
74HC373PW-Q100	NEXPERIA	获取价格	Octal D-type transparent latch; 3-stateProduction
74HC373-Q100	NXP	获取价格	Octal D-type transparent latch; 3-state