Datasheet > 74HC193_13

74HC193_13

更新时间： 2022-04-20 00:39:29

品牌	Logo	应用领域
恩智浦 - NXP		计数器
页数	文件大小	规格书
30页	184K
描述
Presettable synchronous 4-bit binary up/down counter

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74HC193_13 数据手册

74HC193; 74HCT193

NXP Semiconductors

Presettable synchronous 4-bit binary up/down counter

(1)

(2)

CPU

(2)

CPD

TCU

TCD

CLEAR PRESET

(1) Clear overrides load, data and count inputs.

COUNT UP

COUNT DOWN

001aag411

(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input

(CPU) must be HIGH.

Sequence

Clear (reset outputs to zero);

load (preset) to binary thirteen;

count up to fourteen, fifteen, terminal count up, zero, one and two;

count down to one, zero, terminal count down, fifteen, fourteen and thirteen.

Fig 8. Typical clear, load and count sequence

74HC_HCT193

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Product data sheet

Rev. 4 — 24 June 2013

7 of 30

1...4 5 678 9 10...30

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