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74FCT388915T100J8 PDF预览

74FCT388915T100J8

更新时间: 2024-02-21 13:51:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动输出元件逻辑集成电路
页数 文件大小 规格书
10页 1140K
描述
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

74FCT388915T100J8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-28针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.55
其他特性:OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS系列:FCT
输入调节:SCHMITT TRIGGER MUXJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5062 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.032 A
湿度敏感等级:1功能数量:1
反相输出次数:1端子数量:28
实输出次数:7最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:3.3 V传播延迟(tpd):1.3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.8 ns
座面最大高度:4.572 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.5062 mm
最小 fmax:100 MHzBase Number Matches:1

74FCT388915T100J8 数据手册

 浏览型号74FCT388915T100J8的Datasheet PDF文件第4页浏览型号74FCT388915T100J8的Datasheet PDF文件第5页浏览型号74FCT388915T100J8的Datasheet PDF文件第6页浏览型号74FCT388915T100J8的Datasheet PDF文件第7页浏览型号74FCT388915T100J8的Datasheet PDF文件第9页浏览型号74FCT388915T100J8的Datasheet PDF文件第10页 
IDT74FCT388915T  
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)  
COMMERCIALTEMPERATURERANGE  
CPU  
CARD  
CMMU  
CPU  
CMMU  
CMMU  
CMMU  
FCT388915T  
PLL  
CLOCK  
2f  
@f  
SYSTEM  
CLOCK  
SOURCE  
CMMU  
CPU  
CARD  
CMMU  
CPU  
CMMU  
CMMU  
CMMU  
FCT388915T  
PLL  
2f  
CMMU  
DISTRIBUTE  
CLOCK @f  
CLOCK @2f  
at point of use  
FCT388915T  
PLL  
2f  
MEMORY  
CONTROL  
MEMORY  
CARDS  
CLOCK @2f  
at point of use  
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication  
and Low Board-to-Board skew  
FCT388915TSYSTEMLEVELTESTING  
FUNCTIONALITY  
Theserelationshipscanbeseenintheblockdiagram. Arecommendedtest  
configurationwouldbetouseSYNC0orSYNC1asthetestclockinput,andtie  
PLL_ENandREF_SELtogetherandconnectthemtothetestselectlogic.  
WhenthePLL_ENpinisLOW,thePLLisbypassedandtheFCT388915T  
isinlowfrequency"testmode". Intestmode(withFREQ_SELHIGH),the2Q  
outputisinvertedfromtheselectedSYNCinput,andtheQoutputsaredivide-  
by-2(negativeedgetriggered)oftheSYNCinput,andtheQ/2outputisdivide-  
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-  
by-2oftheSYNC,theQoutputsdivide-by-4,andtheQ/2outputdivide-by-8.  
Thisfunctionalityisneededsincemostboard-leveltestersrunat1MHzor  
below,andtheFCT388915Tcannotlockontothatlowofaninputfrequency.  
Inthetestmodedescribedabove,anytestfrequencytestcanbeused.  
8

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