Datasheet > 74FCT388915T100J8

74FCT388915T100J8

更新时间： 2024-02-22 20:56:42

品牌	Logo	应用领域
艾迪悌 - IDT		驱动输出元件逻辑集成电路
页数	文件大小	规格书
10页	1140K
描述
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

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74FCT388915T100J8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	PLASTIC, LCC-28	针数：	28
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.55
其他特性：	OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS	系列：	FCT
输入调节：	SCHMITT TRIGGER MUX	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.5062 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.032 A
湿度敏感等级：	1	功能数量：	1
反相输出次数：	1	端子数量：	28
实输出次数：	7	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	3.3 V	传播延迟（tpd）：	1.3 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.8 ns
座面最大高度：	4.572 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	11.5062 mm
最小 fmax：	100 MHz	Base Number Matches：	1

74FCT388915T100J8 数据手册

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IDT74FCT388915T

3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)

COMMERCIALTEMPERATURERANGE

GENERAL AC SPECIFICATION NOTES (continued):

8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and voltage. The

phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with

the loop filter connection shown in Figure 1 below:

External Loop

Filter

0.1μF

Analog GND

Figure 1

NOTES:

1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free

operation:

a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable

voltage transients at the LF pin.

b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage

transients from the system digital VCC supply and ground planes.

If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 388915T's

digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional protection from the power supply and ground plane transients

that can occur in a high frequency, high speed digital system.

c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.

2. In addition to the bypass capacitors used in the analog filter of Figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board

ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass

capacitors should also be tied as close to the 388915T package as possible.

BOARD VCC

ANALOG VCC

Analog loop filter section

of the FCT388915T

10μF

Low

0.1μF

High

Freq.

Bypass

Freq.

Bypass

0.1μF (Loop

Filter Cap)

ANALOG GND

A separate Analog power supply is not necessary

and should not be used. Following these pre-

scribed guidelines is all that is necessary to use

the FCT388915T in a normal digital environment.

BOARD GND

Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T

1...3 4 567 8 9 10

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与74FCT388915T100J8相关器件

型号	品牌	描述	获取价格	数据表
74FCT388915T100JG	IDT	PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28,	获取价格
74FCT388915T100JG8	IDT	PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28,	获取价格
74FCT388915T100PY8	IDT	PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28,	获取价格
74FCT388915T100PYG	IDT	PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28,	获取价格
74FCT388915T10JG	IDT	3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)	获取价格
74FCT388915T10PY	IDT	3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)	获取价格

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