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74FCT388915T100J8 PDF预览

74FCT388915T100J8

更新时间： 2024-02-21 08:47:09
品牌 Logo 应用领域
艾迪悌 - IDT 驱动输出元件逻辑集成电路
页数 文件大小 规格书
10页 1140K
描述
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

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74FCT388915T100J8 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：PLASTIC, LCC-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.55
其他特性：OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS系列：FCT
输入调节：SCHMITT TRIGGER MUXJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.5062 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.032 A
湿度敏感等级：1功能数量：1
反相输出次数：1端子数量：28
实输出次数：7最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：3.3 V传播延迟（tpd）：1.3 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.8 ns
座面最大高度：4.572 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：11.5062 mm
最小 fmax：100 MHzBase Number Matches：1

74FCT388915T100J8 数据手册

 浏览型号74FCT388915T100J8的Datasheet PDF文件第2页浏览型号74FCT388915T100J8的Datasheet PDF文件第3页浏览型号74FCT388915T100J8的Datasheet PDF文件第4页浏览型号74FCT388915T100J8的Datasheet PDF文件第6页浏览型号74FCT388915T100J8的Datasheet PDF文件第7页浏览型号74FCT388915T100J8的Datasheet PDF文件第8页 
IDT74FCT388915T  
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)  
COMMERCIALTEMPERATURERANGE  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
tRISE/FALL  
AllOutputs  
Parameter  
Condition(1)  
Min.  
0.2(2)  
Max.  
Unit  
Rise/FallTime  
Load = 50Ω to VCC/2, CL = 20pF  
2
ns  
(between0.8Vand2V)  
OutputPulseWidth  
Q, Q, Q/2 outputs(3) Q0-Q4, Q5, Q/2, @ 1.5V  
(3)  
tPULSEWIDTH  
Load = 50Ω to VCC/2, CL = 20pF  
0.5tCYCLE–0.8(5) 0.5tCYCLE+0.8(5)  
0.5tCYCLE–1(5) 0.5tCYCLE+1(5)  
ns  
ns  
ns  
ps  
ps  
ps  
ms  
tPULSEWIDTH  
2QOutput(3)  
tPD  
OutputPulseWidth  
2Q @ 1.5V  
SYNC input to FEEDBACK delay  
Load = 50Ω to VCC/2, CL = 20pF  
+0.1  
—
+1.3  
600  
250  
800  
10  
(3)  
(5)  
SYNC-FEEDBACK (measured at SYNC0 or 1 and FEEDBACK input pins) 0.1µF from LF to Analog GND  
tSKEWr  
(3,4)  
OutputtoOutputSkewbetweenoutputs 2Q,Q0-Q4,  
Q/2(risingedges only)  
Load = 50Ω to VCC/2, CL = 20pF  
(rising)  
tSKEWf  
OutputtoOutputSkew  
—
(3,4)  
(falling)  
betweenoutputsQ0-Q4(fallingedgesonly)  
OutputtoOutputSkew  
tSKEWall(3,4)  
—
2Q, Q/2, Q0-Q4 rising, Q5 falling  
TimerequiredtoacquirePhase-Lockfromtime  
SYNC input signal is received  
OutputEnableTime  
(6)  
(2)  
tLOCK  
1
(2)  
tPZH  
tPZL  
tPHZ  
tPLZ  
3
14  
14  
ns  
ns  
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q  
OutputDisableTime  
(2)  
3
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q  
GENERAL AC SPECIFICATION NOTES:  
1. See test circuit and waveforms.  
2. Minimum limits are guaranteed but not tested.  
3. These specifications are guaranteed but not production tested.  
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.  
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.  
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter  
capacitor shown in Figure 2).  
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable  
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.  
Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC  
frequency range for each possible configuration.  
FREQ_SEL  
Level  
Feedback  
Output  
Q/2  
Allowable SYNC Input  
FrequencyRange(MHZ)  
10to(2x_QfMAX Spec)/4  
20 to (2x_Q fMAX Spec)/2  
20 to (2x_Q fMAX Spec)/2  
40 to (2x_Q fMAX Spec)  
5 to (2x_Q fMAX Spec)/8  
10 to (2x_QfMAX Spec)/4  
10 to (2x_QfMAX Spec)/4  
20 to (2x_Q fMAX Spec)/2  
Corresponding 2Q Output  
FrequencyRange  
Phase Relationship of the Q Outputs  
to Rising SYNC Edge  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
40 to (2Q fMAX Spec)  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
20 to (2QfMAX Spec)/2  
0°  
0°  
Any Q (Q0-Q4)  
Q5  
180°  
0°  
2X_Q  
Q/2  
0°  
LOW  
Any Q (Q0-Q4)  
Q5  
0°  
LOW  
180°  
0°  
LOW  
2X_Q  
5
12345678...10

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