74F273SJX_NL

更新时间： 2024-11-28 13:04:55

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
6页	63K
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数据手册

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74F273SJX_NL 数据手册

April 1988

Revised August 1999

74F273

Octal D-Type Flip-Flop

General Description

Features

■ Ideal buffer for MOS microprocessor or memory

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

The 74F273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

■ Buffered, asynchronous Master Reset

■ See 74F377 for clock enable version

■ See 74F373 for transparent latch version

■ See 74F374 for 3-STATE version

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

Ordering Code:

Order Number Package Number

Package Description

74F273SC

74F273SJ

74F273PC

M20B

M20D

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009511

www.fairchildsemi.com

12 3 4 5 6

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