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74F280DCQR PDF预览

74F280DCQR

更新时间: 2024-11-25 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 76K
描述
Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14

74F280DCQR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.25
其他特性:ODD/EVEN PARITY GENERATOR系列:F/FAST
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.43 mm逻辑集成电路类型:PARITY GENERATOR/CHECKER
位数:9功能数量:1
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

74F280DCQR 数据手册

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April 1988  
Revised September 2000  
74F280  
9-Bit Parity Generator/Checker  
General Description  
The F280 is a high-speed parity generator/checker that  
accepts nine bits of input data and detects whether an  
even or an odd number of these inputs is HIGH. If an even  
number of inputs is HIGH, the Sum Even output is HIGH. If  
an odd number is HIGH, the Sum Even output is LOW. The  
Sum Odd output is the complement of the Sum Even out-  
put.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F280SC  
74F280SJ  
74F280PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009512  
www.fairchildsemi.com  

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