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74AVC16T245DGV PDF预览

74AVC16T245DGV

更新时间： 2024-09-17 11:13:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
22页 306K
描述
16-bit dual supply translating transceiver with configurable voltage translation; 3-stateProduction

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74AVC16T245DGV 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSSOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.58
其他特性：TWO SEPARATE CONFIGURABLE POWER SUPPLY RAILS FOR PORT A AND PORT B系列：AVC
JESD-30 代码：R-PDSO-G48长度：9.7 mm
逻辑集成电路类型：BUS TRANSCEIVER湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：10.2 ns
座面最大高度：1.1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
Base Number Matches：1

74AVC16T245DGV 数据手册

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74AVC16T245  
16-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 7 — 14 January 2019  
Product data sheet  
1. General description  
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state  
outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual  
supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and  
nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control.  
VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making  
the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V,  
1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW  
on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing any damaging backflow current through the device when it is  
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn  
are in the high-impedance OFF-state.  
2. Features and benefits  
•
Wide supply voltage range:  
•
•
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
•
Complies with JEDEC standards:  
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
•
•
ESD protection:  
•
•
•
HBM JESD22-A114F Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101D exceeds 1000 V  
Maximum data rates:  
•
•
•
•
•
•
380 Mbit/s (≥ 1.8 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 2.5 V translation)  
200 Mbit/s (≥ 1.1 V to 1.8 V translation)  
150 Mbit/s (≥ 1.1 V to 1.5 V translation)  
100 Mbit/s (≥ 1.1 V to 1.2 V translation)  
•
•
•
•
•
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
IOFF circuitry provides partial Power-down mode operation  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 
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