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74AVC16T245DGV-Q1J PDF预览

74AVC16T245DGV-Q1J

更新时间: 2024-11-25 20:05:51
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
28页 350K
描述
74AVC16T245-Q100 - 16-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP 48-Pin

74AVC16T245DGV-Q1J 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.25,16
针数:48Reach Compliance Code:compliant
风险等级:5.77控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:AVC
JESD-30 代码:R-PDSO-G48长度:9.7 mm
负载电容(CL):15 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:1.2/3.3 V
Prop。Delay @ Nom-Sup:10.2 ns传播延迟(tpd):10.2 ns
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL翻译:0.8/3.3V &0.8/3.3V
宽度:4.4 mmBase Number Matches:1

74AVC16T245DGV-Q1J 数据手册

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74AVC16T245  
16-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 6 — 9 September 2013  
Product data sheet  
1. General description  
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and  
3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit  
transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit  
input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive  
(nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any  
voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation  
between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH  
on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission  
from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance  
OFF-state  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both nAn and nBn are in the high-impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101D exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (1.8 V to 3.3 V translation)  
200 Mbit/s (1.1 V to 3.3 V translation)  
200 Mbit/s (1.1 V to 2.5 V translation)  
200 Mbit/s (1.1 V to 1.8 V translation)  
150 Mbit/s (1.1 V to 1.5 V translation)  
 
 

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