Datasheet > 74AUP1T08GW

74AUP1T08GW

更新时间： 2022-02-26 12:27:22

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	202K
描述
Low-power 2-input AND gate with voltage-level translator

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74AUP1T08GW 数据手册

Nexperia

74AUP1T08

Low-power 2-input AND gate with voltage-level translator

3 Ordering information

Table 1.ꢀOrdering information

Type number

Package

Temperature

range

Name

Description

Version

74AUP1T08GW -40 °C to +125 °C TSSOP5

74AUP1T08GX -40 °C to +125 °C X2SON5

plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

SOT1226

X2SON5: plastic thermal enhanced extremely

thin small outline package; no leads; 5 terminals;

body 0.8 × 0.8 × 0.35 mm

4 Marking

Table 2.ꢀMarking

Type number

Marking code ^[1]

74AUP1T08GW

74AUP1T08GX

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5 Functional diagram

aaa-027689

aaa-027690

aaa-027691

Figure 1.ꢀLogic symbol

Figure 2.ꢀIEC logic symbol

Figure 3.ꢀLogic diagram

6 Pinning information

6.1 Pinning

74AUP1T08

GND

aaa-027694

Transparent top view

aaa-027693

Figure 4.ꢀPin configuration SOT353-1

Figure 5.ꢀPin configuration SOT1226 (X2SON5)

74AUP1T08

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 23 November 2017

2 / 15

123 4 5 6 7...15

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