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74AUP1G18GW PDF预览

74AUP1G18GW

更新时间: 2024-11-06 11:12:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
19页 281K
描述
Low-power 1-of-2 demultiplexer with 3-state deselected outputProduction

74AUP1G18GW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.16
系列:AUP/ULP/VJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER湿度敏感等级:1
功能数量:1输入次数:1
输出次数:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):18.9 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.25 mm
Base Number Matches:1

74AUP1G18GW 数据手册

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74AUP1G18  
Low-power 1-of-2 demultiplexer with 3-state deselected  
output  
Rev. 8 — 17 July 2023  
Product data sheet  
1. General description  
The 74AUP1G18 is a 1-to-2 demultiplexer with a 3-state outputs. The device buffers the data on  
input A and passes it to output 1Y or 2Y, depending on whether the state of the select input (S) is  
LOW or HIGH. The unused output assumes the high impedence OFF-state. Schmitt-trigger action  
at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very  
low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This  
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables  
the output, preventing the potentially damaging backflow current through the device when it is  
powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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