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74ACTQ273SC PDF预览

74ACTQ273SC

更新时间: 2024-11-13 22:22:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
9页 109K
描述
Quiet Series Octal D-Type Flip-Flop

74ACTQ273SC 数据手册

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August 1989  
Revised November 1999  
74ACTQ273  
Quiet Series Octal D-Type Flip-Flop  
General Description  
Features  
The ACTQ273 has eight edge-triggered D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) and Master Reset (MR) input load and  
reset (clear) all flip-flops simultaneously.  
ICC reduced by 50%  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
The register is fully edge-triggered. The state of each D-  
type input, one setup time before the LOW-to-HIGH clock  
transition, is transferred to the corresponding flip-flop’s Q  
output.  
Buffered common clock and asynchronous master reset  
Outputs source/sink 24 mA  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
4 kV minimum ESD immunity  
The ACTQ utilizes Fairchild Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet Series features  
GTO output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ273SC  
74ACTQ273SJ  
74ACTQ273MTC  
74ACTQ273PC  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0D7  
MR  
Description  
Data Inputs  
Master Reset  
CP  
Clock Pulse Input  
Data Outputs  
Q0Q7  
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010585  
www.fairchildsemi.com  

74ACTQ273SC 替代型号

型号 品牌 替代类型 描述 数据表
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