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74ACTQ273SJ PDF预览

74ACTQ273SJ

更新时间: 2024-10-31 22:35:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 109K
描述
Quiet Series Octal D-Type Flip-Flop

74ACTQ273SJ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.62
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:110000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:110 MHz
Base Number Matches:1

74ACTQ273SJ 数据手册

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August 1989  
Revised November 1999  
74ACTQ273  
Quiet Series Octal D-Type Flip-Flop  
General Description  
Features  
The ACTQ273 has eight edge-triggered D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) and Master Reset (MR) input load and  
reset (clear) all flip-flops simultaneously.  
ICC reduced by 50%  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
The register is fully edge-triggered. The state of each D-  
type input, one setup time before the LOW-to-HIGH clock  
transition, is transferred to the corresponding flip-flop’s Q  
output.  
Buffered common clock and asynchronous master reset  
Outputs source/sink 24 mA  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
4 kV minimum ESD immunity  
The ACTQ utilizes Fairchild Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet Series features  
GTO output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ273SC  
74ACTQ273SJ  
74ACTQ273MTC  
74ACTQ273PC  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0D7  
MR  
Description  
Data Inputs  
Master Reset  
CP  
Clock Pulse Input  
Data Outputs  
Q0Q7  
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010585  
www.fairchildsemi.com  

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