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74ACTQ373QSCX_NL PDF预览

74ACTQ373QSCX_NL

更新时间: 2024-12-01 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
10页 99K
描述
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.150 INCH, LEAD FREE, MO-137, QSOP-20

74ACTQ373QSCX_NL 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:20
Reach Compliance Code:unknown风险等级:5.65
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:8.65 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:3.9116 mmBase Number Matches:1

74ACTQ373QSCX_NL 数据手册

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July 1989  
Revised November 1999  
74ACQ373 74ACTQ373  
Quiet Series Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
ICC and IOZ reduced by 50%  
The ACQ/ACTQ373 consists of eight latches with 3-STATE  
outputs for bus organized system applications. The latches  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data satisfying the input tim-  
ing requirements is latched. Data appears on the bus when  
the Output Enable (OE) is LOW. When OE is HIGH, the  
bus output is in the HIGH impedance state.  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch up immunity  
Eight latches in a single package  
The ACQ/ACTQ373 utilizes Fairchild Quiet Series tech-  
nology to guarantee quiet output switching and improve  
dynamic threshold performance. features GTO output  
control and undershoot corrector in addition to a split  
ground bus for superior performance.  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Outputs source/sink 24 mA  
Faster prop delays than the standard AC/ACT373  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACQ373SC  
74ACQ373SJ  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74ACQ373PC  
74ACTQ373SC  
74ACTQ373SJ  
74ACQT373QSC  
74ACTQ373PC  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MQA20  
N20A  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0D7  
LE  
Description  
Data Inputs  
Latch Enable Input  
OE  
Output Enable Input  
3-STATE Latch Outputs  
O0O7  
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010237  
www.fairchildsemi.com  

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