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SCAS188A − MAY 1991 − REVISED APRIL 1996
54ACT16648 . . . WD PACKAGE
74ACT16648 . . . DL PACKAGE
(TOP VIEW)
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Independent Registers for A and B Buses
Inverting Data Path
D
D
D
D
D
D
D
D
D
1DIR
1OE
1
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1CLKAB
1SAB
GND
1A1
1CLKBA
1SBA
GND
1B1
2
3
Multiplexed Real-Time and Stored Data
4
Flow-Through Architecture Optimizes
PCB Layout
5
1A2
1B2
6
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
V
V
CC
7
CC
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
8
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
9
10
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125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16648 are 16-bit bus transceivers that
V
V
CC
CC
consist of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver. Data
on the A or B bus is clocked into the registers on
the low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the 74ACT16648.
2A7
2A8
GND
2B7
2B8
GND
2SBA
2CLKBA
2OE
2SAB
2CLKAB
2DIR
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
The 74ACT16648 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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1
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