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74ACT16657DLG4 PDF预览

74ACT16657DLG4

更新时间： 2024-11-19 02:58:39
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 150K
描述
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

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中文翻译

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74ACT16657DLG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.7控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：ACT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3/5 VProp。Delay @ Nom-Sup：10.7 ns
传播延迟（tpd）：10.7 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.5 mm

74ACT16657DLG4 数据手册

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54ACT16657, 74ACT16657  
16-BIT TRANSCEIVERS  
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS  
SCAS164A – JANUARY 1991 – REVISED APRIL 1996  
54ACT16657 . . . WD PACKAGE  
74ACT16657 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture Optimizes  
PCB Layout  
1T/R  
1OE  
NC  
1ERR  
GND  
1A1  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1ODD/EVEN  
1PARITY  
GND  
1B1  
1B2  
2
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
3
CC  
4
5
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
6
1A2  
V
7
V
CC  
CC  
500-mA Typical Latch-Up Immunity at  
125°C  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
9
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
description  
The ’ACT16657 contain two noninverting octal  
transceiver sections with separate parity  
generator/checker circuits and control signals.  
For either section, the transmit/receive (1T/R or  
2T/R) input determines the direction of data flow.  
When 1T/R (or 2T/R) is high, data flows from the  
1A (or 2A) port to the 1B (or 2B) port (transmit  
mode); when 1T/R (or 2T/R) is low, data flows  
from the 1B (or 2B) port to the 1A (or 2A) port  
(receive mode). When the output-enable (1OE or  
2OE) input is high, both the 1A (or 2A) and 1B (or  
2B) ports are in the high-impedance state.  
V
V
CC  
CC  
2B7  
2B8  
GND  
2PARITY  
2ODD/EVEN  
2T/R  
2A7  
2A8  
GND  
2ERR  
NC  
2OE  
Odd or even parity is selected by a logic high or  
low level, respectively, on the 1ODD/EVEN (or  
2ODD/EVEN) input. 1PARITY (or 2PARITY)  
carries the parity bit value; it is an output from the  
parity generator/checker in the transmit mode and  
an input to the parity generator/checker in the  
receive mode.  
NC – No internal connection  
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or  
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or  
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on  
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus  
bits plus parity bit) are high.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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74ACT16657DLG4 替代型号

型号 品牌 替代类型 描述 数据表
74ACT16657DLR TI

完全替代

 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
74ACT16657DLRG4 TI

完全替代

 ACT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-
74ACT16652DL TI

功能相似

 16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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