ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢅ
ꢉ
ꢊ
ꢈ ꢋ ꢌꢍꢎ ꢄ ꢍꢏꢐ ꢌꢎꢑꢄ ꢒꢓꢔꢂꢃꢒ ꢔ ꢕꢎ ꢖ ꢌꢔ ꢕꢗ ꢖ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢅ
ꢐ
ꢐ
ꢘ
ꢎ
ꢄ
ꢙ
ꢚ
ꢌ
ꢐ
ꢄ
ꢂ
ꢄ
ꢒ
ꢗ
ꢏ
ꢄ
ꢖ
ꢏ
ꢄ
SCAS176A − JANUARY 1991 − REVISED APRIL 1996
54ACT16821 . . . WD PACKAGE
74ACT16821 . . . DL PACKAGE
(TOP VIEW)
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
D
D
Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
1OE
1Q1
1Q2
GND
1Q3
1Q4
1CLK
1D1
1D2
GND
1D3
1D4
1
56
55
54
53
52
51
50
49
48
47
46
45
2
3
D
D
D
D
Flow-Through Architecture Optimizes
PCB Layout
4
5
6
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
V
V
7
CC
CC
1Q5
1Q6
1Q7
GND
1Q8
1D5
1D6
1D7
GND
1D8
8
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include 300-mil Shrink
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
9
10
11
12
1Q9 13
1Q10 14
2Q1 15
2Q2 16
2Q3 17
GND 18
2Q4 19
2Q5 20
2Q6 21
44 1D9
43 1D10
42 2D1
41 2D2
40 2D3
39 GND
38 2D4
37 2D5
36 2D6
description
These 20-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, parity bus interfacing, and
working registers.
22
23
24
25
26
27
28
35
34
33
32
31
30
29
V
V
CC
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
2D7
2D8
GND
2D9
2D10
2CLK
The ’ACT16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs
follow the data (D) inputs. Each 10-bit flip-flop
section has a buffered output-enable (1OE or
2OE) input that can be used to place the ten
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16821 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16821 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16821 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢏ ꢑ ꢕꢒꢐꢐ ꢗ ꢄꢙ ꢒꢓꢘ ꢎꢐ ꢒ ꢑ ꢗꢄꢒꢛ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢖꢓ ꢗ ꢛ ꢏ ꢃꢄ ꢎꢗ ꢑ
ꢭ
ꢛ
ꢂ
ꢄ
ꢂ
ꢞ
ꢦ
ꢨ
ꢡ
ꢩ
ꢤ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢢ
ꢣ
ꢩ
ꢩ
ꢥ
ꢦ
ꢜ
ꢧ
ꢟ
ꢡ
ꢨ
ꢪ
ꢣ
ꢫ
ꢬ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢠ
ꢧ
ꢜ
ꢥ
ꢖ
ꢩ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢟ
ꢢ
ꢡ
ꢦ
ꢨ
ꢡ
ꢩ
ꢤ
ꢜ
ꢡ
ꢟ
ꢪ
ꢥ
ꢢ
ꢞ
ꢨ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢟ
ꢪ
ꢥ
ꢩ
ꢜ
ꢝ
ꢥ
ꢜ
ꢥ
ꢩ
ꢤ
ꢟ
ꢡ
ꢨ
ꢄ
ꢥ
ꢮ
ꢧ
ꢟ
ꢎ
ꢦ
ꢟ
ꢜ
ꢩ
ꢣ
ꢤ
ꢥ
ꢦ
ꢜ
ꢟ
ꢟ
ꢜ
ꢧ
ꢦ
ꢠ
ꢧ
ꢩ
ꢠ
ꢯ
ꢧ
ꢩ
ꢩ
ꢧ
ꢦ
ꢜ
ꢰ
ꢭ
ꢖ
ꢩ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢞ
ꢪꢧ ꢩ ꢧ ꢤ ꢥ ꢜ ꢥ ꢩ ꢟ ꢭ
ꢡ
ꢦ
ꢪ
ꢩ
ꢡ
ꢢ
ꢥ
ꢟ
ꢟ
ꢞ
ꢦ
ꢱ
ꢠ
ꢡ
ꢥ
ꢟ
ꢦ
ꢡ
ꢜ
ꢦ
ꢥ
ꢢ
ꢥ
ꢟ
ꢟ
ꢧ
ꢩ
ꢞ
ꢬ
ꢰ
ꢞ
ꢦ
ꢢ
ꢬ
ꢣ
ꢠ
ꢥ
ꢜ
ꢥ
ꢟ
ꢜ
ꢞ
ꢦ
ꢱ
ꢡ
ꢨ
ꢧ
ꢬ
ꢬ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
5秒后页面跳转
深入解析CS8416引脚说明、参数、技术特点
TPA3116D2功放芯片参数详解、引脚说明
移位寄存器74HC165引脚说明、驱动程序示例解读
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
