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74ACT16833

更新时间： 2024-11-21 12:50:35
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
9页 172K
描述
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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74ACT16833 数据手册

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SCAS166A − JUNE 1990 − REVISED APRIL 1996  
54ACT16833 . . . WD PACKAGE  
74ACT16833 . . . DL PACKAGE  
(TOP VIEW)  
D
Members of the Texas Instruments  
WidebusFamily  
Inputs Are TTL-Voltage Compatible  
D
D
Parity Error Flag With Parity  
Generator/Checker  
1OEB  
1CLK  
1ERR  
GND  
1A1  
1OEA  
1CLR  
1PARITY  
GND  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
2
D
D
Register for Storage of the Parity Error Flag  
3
4
Flow-Through Architecture Optimizes  
PCB Layout  
1B1  
5
1A2  
1B2  
6
D
D
D
D
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
8
EPIC(Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
9
10  
11  
12  
13  
14  
15  
16  
17  
125°C  
Package Options Include 300-mil Shrink  
Small-Outline (DL) Packages Using 25-mil  
Center-to-Center Pin Spacings and 380-mil  
Fine-Pitch Ceramic Flat (WD) Packages  
Using 25-mil Center-to-Center Pin Spacings  
GND 18  
2A4 19  
2A5 20  
2A6 21  
39 GND  
38 2B4  
37 2B5  
36 2B6  
description  
The ’ACT16833 consist of two noninverting 8-bit  
to 9-bit parity bus transceivers and are designed  
for communication between data buses. For each  
transceiver, when data is transmitted from the  
A bus to the B bus, an odd-parity bit is generated  
and output on the parity I/O pin (1PARITY or  
2PARITY). When data is transmitted from the  
B bus to the A bus, 1PARITY or 2PARITY is  
configured as an input and combined with the  
B-input data to generate an active-low error flag if  
odd parity is not detected.  
V
22  
35  
V
CC  
CC  
2A7 23  
34 2B7  
2A8 24  
33 2B8  
GND 25  
2ERR 26  
2CLK 27  
32 GND  
31 2PARITY  
30 2CLR  
28  
29  
2OEB  
2OEA  
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity error flag is  
clocked into 1ERR or 2ERR on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR or 2ERR is  
cleared (set high) by taking the clear (1CLR or 2CLR) input low.  
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively  
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity  
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic  
capability.  
The 74ACT16833 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and  
functionality of standard small-outline packages in the same printed-circuit-board area.  
The 54ACT16833 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74ACT16833 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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