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74ACT16841DLRG4 PDF预览

74ACT16841DLRG4

更新时间： 2024-01-28 03:49:45
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德州仪器 - TI 锁存器输出元件
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9页 309K
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20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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74ACT16841DLRG4 数据手册

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54ACT16841, 74ACT16841  
20-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS174A – MAY 1991 – REVISED APRIL 1996  
54ACT16841 . . . WD PACKAGE  
74ACT16841 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
3-State Outputs Drive Bus Lines Directly  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
Provide Extra Bus Driving/Latches  
Necessary for Wider Address/Data Paths or  
Buses With Parity  
2
3
4
5
Flow-Through Architecture Optimizes  
PCB Layout  
6
7
V
V
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
CC  
CC  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) Packages,  
300-mil Shrink Small-Outline (DL) Packages  
Using 25-mil Center-to-Center Pin  
Spacings, and 380-mil Fine-Pitch Ceramic  
Flat (WD) Packages Using 25-mil  
Center-to-Center Pin Spacings  
description  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
These 20-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
The ’ACT16841 can be used as two 10-bit latches  
or one 20-bit latch. The 20 latches are transparent  
D-type. While the latch-enable (1LE or 2LE) input  
is high, the Q outputs of the corresponding 10-bit  
latch follow the data (D) inputs. When LE is taken  
low, the Q outputs are latched at the levels that  
were set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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