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74ACT16841DL PDF预览

74ACT16841DL

更新时间： 2024-01-07 04:55:37
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 116K
描述
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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74ACT16841DL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.38控制类型：ENABLE LOW/HIGH
系列：ACTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.41 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：10功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：12.2 ns
传播延迟（tpd）：12.7 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.49 mmBase Number Matches：1

74ACT16841DL 数据手册

 浏览型号74ACT16841DL的Datasheet PDF文件第2页浏览型号74ACT16841DL的Datasheet PDF文件第3页浏览型号74ACT16841DL的Datasheet PDF文件第4页浏览型号74ACT16841DL的Datasheet PDF文件第5页浏览型号74ACT16841DL的Datasheet PDF文件第6页 
54ACT16841, 74ACT16841  
20-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS174A – MAY 1991 – REVISED APRIL 1996  
54ACT16841 . . . WD PACKAGE  
74ACT16841 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
3-State Outputs Drive Bus Lines Directly  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
Provide Extra Bus Driving/Latches  
Necessary for Wider Address/Data Paths or  
Buses With Parity  
2
3
4
5
Flow-Through Architecture Optimizes  
PCB Layout  
6
7
V
V
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
CC  
CC  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) Packages,  
300-mil Shrink Small-Outline (DL) Packages  
Using 25-mil Center-to-Center Pin  
Spacings, and 380-mil Fine-Pitch Ceramic  
Flat (WD) Packages Using 25-mil  
Center-to-Center Pin Spacings  
description  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
These 20-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
The ’ACT16841 can be used as two 10-bit latches  
or one 20-bit latch. The 20 latches are transparent  
D-type. While the latch-enable (1LE or 2LE) input  
is high, the Q outputs of the corresponding 10-bit  
latch follow the data (D) inputs. When LE is taken  
low, the Q outputs are latched at the levels that  
were set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

中文翻译

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74ACT16841DL 替代型号

型号 品牌 替代类型 描述 数据表
74ACT16841DLR TI

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 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
74ACT16841DLG4 TI

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