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74ACT11657

更新时间： 2024-11-18 12:21:31
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 120K
描述
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS

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中文翻译

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74ACT11657 数据手册

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SCAS232 − AUGUST 1992 − REVISED APRIL 1993  
DW PACKAGE  
(TOP VIEW)  
• Inputs Are TTL-Voltage Compatible  
• Flow-Through Architecture Optimizes  
PCB Layout  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
PARITY  
A1  
OE  
B1  
B2  
B3  
B4  
• Center-Pin V  
and GND Pin  
Configurations Minimize High-Speed  
Switching Noise  
CC  
2
3
A2  
A3  
A4  
GND  
GND  
GND  
GND  
A5  
A6  
A7  
A8  
ERR  
4
• EPIC(Enhanced-Performance Implanted  
5
CMOS) 1-µm Process  
6
V
V
V
CC  
CC  
CC  
7
• 500-mA Typical Latch-Up Immunity  
at 125°C  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
8
9
B5  
10  
11  
12  
13  
14  
B6  
B7  
B8  
ODD/EVEN  
T/R  
description  
The 74ACT11657 contains eight noninverting  
buffers with 3-state outputs and an 8-bit parity  
generator/checker and is intended for bus-  
oriented applications.  
The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceivers.  
When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from  
the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are  
in the high-impedance state.  
Odd or even parity is selected by a logic high or low level, respectively, on the ODD/EVEN input. PARITY carries  
the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity  
generator/checker in the receive mode.  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN  
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level  
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the ERR output logic level  
indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN  
is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR is low,  
indicating a parity error.  
The 74ACT11657 is characterized for operation from −40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
12345678

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与74ACT11657相关器件

型号 品牌 获取价格 描述 数据表
74ACT11657D YAGEO

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 		Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO28
74ACT11657D-T YAGEO

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 		Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO28
74ACT11657DW TI

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 		Octal Parity Bus Transceivers 28-SOIC -40 to 85
74ACT11657DWR TI

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 		Octal Parity Bus Transceivers 28-SOIC -40 to 85
74ACT11657J TI

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 		IC,BUS TRANSCEIVER,SINGLE,8-BIT,ACT-CMOS,DIP,28PIN,CERAMIC
74ACT11657N TI

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 		IC,BUS TRANSCEIVER,SINGLE,8-BIT,ACT-CMOS,DIP,28PIN,PLASTIC
74ACT11657N YAGEO

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 		Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDIP28
74ACT11800DW ETC

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 		LOGIC GATE|3 4-IN AND/NAND|ACT-CMOS|SOP|24PIN|PLASTIC
74ACT11800DWR TI

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 		ACT SERIES, TRIPLE 4-INPUT AND/NAND GATE, PDSO24, PLASTIC, SO-24
74ACT11800NT ETC

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 		LOGIC GATE|3 4-IN AND/NAND|ACT-CMOS|DIP|24PIN|PLASTIC

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